Cache memories are the dominant source of soft-error vulnerability in modern computing systems, contributing most of the processor-level failure rate in RISC-V architectures deployed in fault-prone environments. In these systems, a standard approach to protect multilevel caches is to mix Error Detection and Correction (EDAC) schemes: parity for the L1 instruction cache and SEC-DED codes for the L1 data and unified L2 cache.
This work introduces ENGAGE-V, a fully RERI-compliant RAS interface engineered to monitor a heterogeneous multilevel EDAC-protected cache hierarchy in a RISC-V system. The implementation adds a cache-aware Pre-Process stage with multi-channel severity-and-priority arbitration of newly detected errors and a configurable Evaluator for containability and deferrability assessment. A per-cache RERI event classification is also derived to map every combination of the EDAC scheme and fault multiplicity to its severity and recoverability. The embedded cache linefill functionality is leveraged to retrieve erroneous-but-clean cache data words and optimize system RAS (Reliability, Availability, Serviceability) capabilities. Standard-cell synthesis at 7nm shows that the same microarchitecture is portable across Embedded, Application, and HPC grade operating profiles through a small set of implementation-time parameters, with an area overhead that scales linearly with the Error Record Bank depth and an end-to-end log & report latency bounded to a few clock cycles.

Keywords: EDAC-Protected Cache, Error Logging, Fault Tolerance, Multilevel Cache Reliability, RAS, RISC-V, RERI

DOI: in press...